1. Field of the Invention
The present invention relates to a floor-planning system to predetermine the layout based on a block diagram at the initial stage in development of circuits such as LSI and PCB.
2. Description of the Prior Art
Conventionally, in the initial stage of designing for an LSI or other devices using a block diagram where logical connection information is not yet fixed, the block layout is not estimated and the feasibility on the applicable LSI or PCB is not judged in many cases. Even when such block layout estimation and feasibility judgment are performed, they are just studied by the designer on paper.
Thus, in such initial stage of LSI designing using a block diagram, it is not clear whether the subject to be designed and fulfilled can be accommodated in the applicable LSI chip or PCB with limited space or other restrictions. It is quite difficult to judge the feasibility of a design in such an initial stage of designing. On the other hand, if the impossibility of accommodation is found only in the layout estimation at the detail designing stage or physical design stage where feasibility on LSI or PCB becomes clear, the designer has to try to realize the design by reducing some functions or adopting another LSI or PCB.
However, at such detail designing or physical design stage, other LSIs and PCBs have also been designed; design modification as above requires re-designing in a large scale for a plurality of LSIs or PCBs, which largely influences the entire designing process. Further, it is preferred in LSI designing to route the wirings for reducing delay time of signals. Specifically, layouts having short wirings without intersections or detours which enable natural signal flow are preferred. However, such connection status of wirings is not considered in the initial designing stage and a problem may be found in the detail designing or physical design stage as described above, which requires design change.